System-on-chip (SoC) requires precision resistors integrated with complementary metal-oxide-semiconductor (CMOS). However, conventional poly resistors are no longer feasible due to incompatibility with HKMG technology. A middle-of-line (MOL) resistor metal (RM) is an option, since they are compatible with HKMG, but are formed above the interlayer dielectric (ILD) causing topography issues and incompatibility with self-aligned contact (SAC).
A need therefore exists for devices with improved RM integration to resolve topography and incompatibility issues, and for enabling methodology.